The CMOS circuits of current semiconductor technology comprise n-type FETs (nFETs), which utilize electron carriers for their operation, and p-type FETs (pFETs), which utilize hole carriers for their operation. CMOS circuits are typically fabricated on semiconductor wafers having a single crystal orientation. In particular, most of today's semiconductor devices are built on Si having a (100) surface orientation.
It is known that electrons have a high mobility in Si with a (100) surface orientation and that holes have high mobility in Si with a (110) surface orientation. In fact, hole mobility can be about 2 to 4 times higher on a 110-oriented Si wafer than on a standard 100-oriented Si wafer. It would therefore be desirable to create a hybrid-orientation substrate comprising 100-oriented Si (where nFETs would be formed) and 110-oriented Si (where pFETs would be formed).
Planar hybrid substrate structures with different surface orientations have been described previously (see, for example, co-assigned U.S. application Ser. No. 10/696,634, filed Oct. 29, 2003, and co-assigned U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003).
FIGS. 1A-1E show, in cross section view, some prior art examples of planar hybrid-orientation semiconductor substrate structures comprising bulk semiconductor substrate 10, dielectric trench isolation regions 20, semiconductor regions 30 with a first surface orientation (e.g., j′k′l′), and semiconductor region 40 with a second surface orientation (e.g., jkl). In the structure of FIG. 1A, semiconductor regions 30 and 40 are both directly on bulk substrate 10, with semiconductor region 40 and bulk substrate 10 having the same orientation. The structure of FIG. 1B differs from that of FIG. 1A only in that semiconductor regions 30 are on buried oxide (BOX) layer 50 instead of directly on bulk substrate 10. The structures of FIGS. 1C-1E differ from those of FIGS. 1A-1B by the thickness of BOX layers 50 and 50′ and by the depth of trench isolation structures 20 and 20′.
FIGS. 2A-2B show, in cross section view, previous examples of how integrated CMOS circuits comprising at least one pFET on a (110) crystallographic plane of Si and at least one NFET on a (100) crystallographic plane of Si may be advantageously disposed on the hybrid-orientation substrate structure of FIG. 1B. In FIG. 2A, a bulk Si substrate 120 with 100 orientation has regions 130 of 110-oriented Si on BOX layer 140, and regions 150 of regrown 100-oriented Si on bulk substrate 120. pFET devices 170 are disposed on 110-oriented regions 130 and nFET devices 180 are disposed on 100-oriented regions 150. In FIG. 2B, a bulk Si substrate 180 with 110 orientation has regions 190 of 100-oriented Si on a BOX layer 140 and regions 200 of regrown 110-oriented Si on bulk substrate 180. pFET devices 210 are disposed on 110-oriented regions 180 and nFEET devices 220 are disposed on 100-oriented regions 190.
FIGS. 3A-3I show, in cross section view, the steps of a prior art method used to form the structure of FIG. 1B. Specifically, FIG. 3A shows the starting Si substrate 250, and FIG. 3B shows substrate 250 after formation of BOX layer 260 and silicon-on-insulator (SiOI) device layer 270. Si substrate 250 may be 110- (or 100-) oriented, and SiOI device layer 270 would be 100- (or 110-) oriented. SiOI layer 270 may be formed by bonding or other methods. After depositing protective dielectric (preferably SiNx) layer 280 to form the structure of FIG. 3C, SiOI device layer 270 and BOX layer 260 are removed in selected areas to form openings 290 extending to Si substrate 250, as shown in FIG. 3D. Openings 290 are lined with a dielectric (preferably SiNx) which is then etched to form sidewall spacers 300, as shown in FIG. 3E. Next, epitaxial Si 310 is selectively grown in openings 290 to produce the structure of FIG. 3F, which is planarized back to form the structure of FIG. 3G. Protective dielectric 280 is then removed by a process such as polishing to form the structure of FIG. 3H with coplanar, differently oriented Si device layers 310 (on bulk Si substrate 250) and 320 (on BOX layer 260). FIG. 3I shows the completed substrate structure after shallow trench isolation areas 330 have been formed in the structure of FIG. 3H.
However, for many applications, it would be desirable to have both of the differently oriented Si regions on a BOX. Such structures are possible, but not easy, to produce by variations of the method of FIGS. 3A-3I. For example, the structure of FIG. 4 may be produced by replacing Si substrate 250 in FIG. 3A with a SiOI substrate 400 comprising substrate 410, BOX layer 420, and Si layer 430 to produce differently oriented single crystal regions 320 with a first orientation and 440 with a second orientation matching that of semiconductor layer 430. However, the use of two BOX layers adds extra complexity to the process and produces structures where one of the hybrid orientations is significantly thicker than the other (a disadvantage when both layers need to be thin). In addition, selective epitaxial Si growth can be tricky; defects are likely to nucleate on the sides of sidewall spacers 300 (shown in FIGS. 3E-3F), especially when openings 290 are small (e.g., less than 500 nm in diameter).
In view of the above, it would be desirable to have simpler and better methods (i.e., those that do not require epitaxial regrowth) to form planar hybrid-orientation semiconductor substrate structures, especially planar hybrid-orientation semiconductor-on-insulator (SOI) substrate structures wherein the differently oriented semiconductors are disposed on a common BOX layer.
In addition, it would be desirable to have integrated electrical circuits on such planar hybrid-orientation SOI substrates wherein the electrical circuits comprise pFETs on a (110) crystallographic plane and nFETs on a (100) crystallographic plane.